library verilog;
use verilog.vl_types.all;
entity ifu is
    port(
        nPC_sel         : in     vl_logic_vector(1 downto 0);
        zero            : in     vl_logic_vector(31 downto 0);
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        instruction     : out    vl_logic_vector(31 downto 0);
        j_sel           : in     vl_logic;
        jValue          : in     vl_logic_vector(25 downto 0)
    );
end ifu;
